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Icarus Verilog的使用 - zhuangzhuang1988 - 博客园
test.vcd是文本文件！看文本比看波形习惯多了。
#16 b110 ! b110 % b1000000 # b1000000 $
dsn也是文本文件！像是一堆汇编代码，vvp是个虚拟机。
T_0 ; %wait E_0000027bce8b8b70; %pushi/vec4 0, 0, 4; %store/vec4 v0000027bce8bae90_0, 0, 4; %load/vec4 v0000027bce8baf30_0; %flag_set/vec4 8; %jmp/0xz T_0.0, 8; %load/vec4 v0000027bce6e2e10_0; %cmpi/e 2, 0, 16; %jmp/0xz T_0.2, 4; %pushi/vec4 1, 0, 4; %store/vec4 v0000027bce8bae90_0, 0, 4; T_0.2 ;
gtkwave里一堆东西, 158MB. iverilog 31.7MB. Fliplot is an alternative to GTKWave, but this is implemented in HTML, Javascript and Python, which make Fliplot scriptable, pluginable, portable. [当我没写，这个也很啰嗦]
vcdvcd · PyPI
1 counter_tb.clock 2 counter_tb.enable 3 counter_tb.out[1:0] 4 counter_tb.reset 5 counter_tb.top.out[1:0] 0 1 2 3 4 5 =========== 0 1 0 x 0 x 1 0 0 x 1 x 2 1 0 0 1 0
While simulating logic circuits, the values of signals can be written out to a Value Change Dump (VCD) file. Verilog_VCD can be used to parse a VCD file so that further analysis can be performed on the simulation data. The entire VCD file can be stored in a Python data structure and manipulated using standard hash and array operations.
Matplotlib is a comprehensive library for creating static, animated, and interactive visualizations in Python.
verilog vcd file format specification
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